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INCLUDED FROM


   1 /*
   2  * fiwix/include/fiwix/ide.h
   3  *
   4  * Copyright 2018-2021, Jordi Sanfeliu. All rights reserved.
   5  * Distributed under the terms of the Fiwix License.
   6  */
   7 
   8 #ifndef _FIWIX_IDE_H
   9 #define _FIWIX_IDE_H
  10 
  11 #include <fiwix/fs.h>
  12 #include <fiwix/part.h>
  13 #include <fiwix/sigcontext.h>
  14 #include <fiwix/sleep.h>
  15 
  16 #define IDE0_IRQ                14      /* primary controller interrupt */
  17 #define IDE1_IRQ                15      /* secondary controller interrupt */
  18 
  19 #define IDE0_MAJOR              3       /* 1st controller major number */
  20 #define IDE1_MAJOR              22      /* 2nd controller major number */
  21 #define IDE_MINORS              4       /* max. minors/partitions per unit */
  22 #define IDE_MASTER_MSF          0       /* IDE master minor shift factor */
  23 #define IDE_SLAVE_MSF           6       /* IDE slave minor shift factor */
  24 
  25 #define IDE_PRIMARY             0
  26 #define IDE_SECONDARY           1
  27 #define IDE_MASTER              0
  28 #define IDE_SLAVE               1
  29 #define IDE_ATA                 0
  30 #define IDE_ATAPI               1
  31 
  32 #define NR_IDE_CTRLS            2       /* IDE controllers */
  33 #define NR_IDE_DRVS             2       /* max. drives per IDE controller */
  34 
  35 /* controller addresses */
  36 #define IDE0_BASE               0x1F0   /* primary controller base addr */
  37 #define IDE0_CTRL               0x3F4   /* primary controller control port */
  38 #define IDE1_BASE               0x170   /* secondary controller base addr */
  39 #define IDE1_CTRL               0x374   /* secondary controller control port */
  40 
  41 #define IDE_BASE_LEN            7       /* controller address length */
  42 
  43 #define IDE_RDY_RETR_LONG       50000   /* long delay for fast CPUs */
  44 #define IDE_RDY_RETR_SHORT      500     /* short delay for slow CPUs */
  45 #define MAX_IDE_ERR             10      /* number of retries */
  46 #define MAX_CD_ERR              5       /* number of retries in CDROMs */
  47 
  48 #define SET_IDE_RDY_RETR(retries)                                       \
  49         if((cpu_table.hz / 1000000) <= 100) {                           \
  50                 retries = IDE_RDY_RETR_SHORT;                           \
  51         } else {                                                        \
  52                 retries = IDE_RDY_RETR_LONG;                            \
  53         }
  54 
  55 #define WAIT_FOR_IDE    (1 * HZ)        /* timeout for hard disk */
  56 #define WAIT_FOR_CD     (3 * HZ)        /* timeout for cdrom */
  57 
  58 /* controller registers */
  59 #define IDE_DATA                0x0     /* Data Port Register (R/W) */
  60 #define IDE_ERROR               0x1     /* Error Register (R) */
  61 #define IDE_FEATURES            0x1     /* Features Register (W) */
  62 #define IDE_SECCNT              0x2     /* Sector Count Register (R/W) */
  63 #define IDE_SECNUM              0x3     /* Sector Number Register (R/W) */
  64 #define IDE_LCYL                0x4     /* Cylinder Low Register (R/W) */
  65 #define IDE_HCYL                0x5     /* Cylinder High Register (R/W) */
  66 #define IDE_DRVHD               0x6     /* Drive/Head Register (R/W) */
  67 #define IDE_STATUS              0x7     /* Status Register (R) */
  68 #define IDE_COMMAND             0x7     /* Command Register (W) */
  69 
  70 #define IDE_ALT_STATUS          0x2     /* Alternate Register (R) */
  71 #define IDE_DEV_CTRL            0x2     /* Device Control Register (W) */
  72 
  73 /* error register bits */
  74 #define IDE_ERR_AMNF            0x01    /* Address Mark Not Found */
  75 #define IDE_ERR_TK0NF           0x02    /* Track 0 Not Found */
  76 #define IDE_ERR_ABRT            0x04    /* Aborted Command */
  77 #define IDE_ERR_MCR             0x08    /* Media Change Registered */
  78 #define IDE_ERR_IDNF            0x10    /* Sector ID Field Not Found */
  79 #define IDE_ERR_MC              0x20    /* Media Changed */
  80 #define IDE_ERR_UNC             0x40    /* Uncorrectable Data Error */
  81 #define IDE_ERR_BBK             0x80    /* Bad Block */
  82 
  83 /* status register bits */
  84 #define IDE_STAT_ERR            0x01    /* an error ocurred */
  85 #define IDE_STAT_SENS           0x02    /* sense data available */
  86 #define IDE_STAT_CORR           0x04    /* a correctable error ocurred */
  87 #define IDE_STAT_DRQ            0x08    /* device is ready to transfer */
  88 #define IDE_STAT_DSC            0x10    /* device requests service o intr. */
  89 #define IDE_STAT_DWF            0x20    /* drive write fault */
  90 #define IDE_STAT_RDY            0x40    /* drive is ready */
  91 #define IDE_STAT_BSY            0x80    /* drive is busy */
  92 
  93 #define IDE_CHS_MODE            0xA0    /* select CHS mode */
  94 #define IDE_LBA_MODE            0xE0    /* select LBA mode */
  95 
  96 /* alternate & device control register bits */
  97 #define IDE_DEVCTR_DRQ          0x08    /* Data Request */
  98 #define IDE_DEVCTR_NIEN         0x02    /* Disable Interrupt */
  99 #define IDE_DEVCTR_SRST         0x04    /* Software Reset */
 100 
 101 /* ATA commands */
 102 #define ATA_READ_PIO            0x20    /* read sector(s) with retries */
 103 #define ATA_READ_MULTIPLE_PIO   0xC4    /* read multiple sectors */
 104 #define ATA_WRITE_PIO           0x30    /* write sector(s) with retries */
 105 #define ATA_WRITE_MULTIPLE_PIO  0xC5    /* write multiple sectors */
 106 #define ATA_SET_MULTIPLE_MODE   0xC6
 107 #define ATA_PACKET              0xA0
 108 #define ATA_IDENTIFY_PACKET     0xA1    /* identify ATAPI device */
 109 #define ATA_IDENTIFY            0xEC    /* identify ATA device */
 110 
 111 /* ATAPI commands */
 112 #define ATAPI_TEST_UNIT         0x00
 113 #define ATAPI_REQUEST_SENSE     0x03
 114 #define ATAPI_START_STOP        0x1B
 115 #define ATAPI_MEDIUM_REMOVAL    0x1E
 116 #define ATAPI_READ10            0x28
 117 
 118 #define CD_UNLOCK_MEDIUM        0x00    /* allow medium removal */
 119 #define CD_LOCK_MEDIUM          0x01    /* prevent medium removal */
 120 #define CD_EJECT                0x02    /* eject the CD if possible */
 121 #define CD_LOAD                 0x03    /* load the CD (closes tray) */
 122 
 123 /* ATAPI CD additional sense code */
 124 #define ASC_NOT_READY           0x04
 125 #define ASC_NO_MEDIUM           0x3A
 126 
 127 /* capabilities */
 128 #define IDE_SUPPORTS_CFA        0x848A
 129 #define IDE_HAS_DMA             0x100
 130 #define IDE_HAS_LBA             0x200
 131 #define IDE_MIN_LBA             16514064/* sectors limit for using CHS */
 132 
 133 /* general configuration bits */
 134 #define IDE_HAS_UDMA            0x04    /* device supports UDMA */
 135 #define IDE_REMOVABLE           0x80    /* removable media device */
 136 
 137 /* ATAPI types */
 138 #define ATAPI_IS_SEQ_ACCESS     0x01    /* sequential-access device */
 139 #define ATAPI_IS_PRINTER        0x02
 140 #define ATAPI_IS_PROCESSOR      0x03
 141 #define ATAPI_IS_WRITE_ONCE     0x04
 142 #define ATAPI_IS_CDROM          0x05
 143 #define ATAPI_IS_SCANNER        0x06
 144 
 145 /* IDE drive flags */
 146 #define DEVICE_IS_ATAPI         0x01
 147 #define DEVICE_IS_CFA           0x02
 148 #define DEVICE_IS_DISK          0x04
 149 #define DEVICE_IS_CDROM         0x08
 150 #define DEVICE_REQUIRES_LBA     0x10
 151 #define DEVICE_HAS_RW_MULTIPLE  0x20
 152 
 153 /* ATA/ATAPI-4 based */
 154 struct ide_drv_ident {
 155         unsigned short int gen_config;          /* general configuration bits */
 156         unsigned short int logic_cyls;          /* logical cylinders */
 157         unsigned short int reserved2;
 158         unsigned short int logic_heads;         /* logical heads */
 159         unsigned short int retired4;
 160         unsigned short int retired5;
 161         unsigned short int logic_spt;           /* logical sectors/track */
 162         unsigned short int retired7;
 163         unsigned short int retired8;
 164         unsigned short int retired9;
 165         char serial_number[20];                 /* serial number */
 166         unsigned short int vendor_spec20;
 167         unsigned short int buffer_cache;
 168         unsigned short int vendor_spec22;       /* reserved */
 169         char firmware_rev[8];                   /* firmware version */
 170         char model_number[40];                  /* model number */
 171         unsigned short int rw_multiple;
 172         unsigned short int reserved48;
 173         unsigned short int capabilities;        /* capabilities */
 174         unsigned short int reserved50;
 175         unsigned short int pio_mode;            /* PIO data transfer mode*/
 176         unsigned short int dma_mode;
 177         unsigned short int fields_validity;     /* fields validity */
 178         unsigned short int cur_log_cyls;        /* current logical cylinders */
 179         unsigned short int cur_log_heads;       /* current logical heads */
 180         unsigned short int cur_log_spt;         /* current logical sectors/track */
 181         unsigned short int cur_capacity;        /* current capacity in sectors */
 182         unsigned short int cur_capacity2;       /* 32bit number */
 183         unsigned short int mult_sect_set;       /* multiple sector settings */
 184         unsigned short int tot_sectors;         /* sectors (LBA only) */
 185         unsigned short int tot_sectors2;        /* 32bit number */
 186         unsigned short int singleword_dma;
 187         unsigned short int multiword_dma;       /* multiword DMA settings */
 188         unsigned short int adv_pio_modes;       /* advanced PIO modes */
 189         unsigned short int min_multiword;       /* min. Multiword DMA transfer */
 190         unsigned short int rec_multiword;       /* recommended Multiword DMS transfer */
 191         unsigned short int min_pio_wo_fc;       /* min. PIO w/o flow control */
 192         unsigned short int min_pio_w_fc;        /* min. PIO with flow control */
 193         unsigned short int reserved69;
 194         unsigned short int reserved70;
 195         unsigned short int reserved71;
 196         unsigned short int reserved72;
 197         unsigned short int reserved73;
 198         unsigned short int reserved74;
 199         unsigned short int queue_depth;         /* queue depth */
 200         unsigned short int reserved76;
 201         unsigned short int reserved77;
 202         unsigned short int reserved78;
 203         unsigned short int reserved79;
 204         unsigned short int majorver;            /* major version number */
 205         unsigned short int minorver;            /* minor version number */
 206         unsigned short int cmdset1;             /* command set supported */
 207         unsigned short int cmdset2;             /* command set supported */
 208         unsigned short int cmdsf_ext;           /* command set/feature sup.ext. */
 209         unsigned short int cmdsf_enable1;       /* command s/f enabled */
 210         unsigned short int cmdsf_enable2;       /* command s/f enabled */
 211         unsigned short int cmdsf_default;       /* command s/f default */
 212         unsigned short int ultradma;            /* ultra DMA mode */
 213         unsigned short int reserved89;
 214         unsigned short int reserved90;
 215         unsigned short int curapm;              /* current APM values */
 216         unsigned short int reserved92_126[35];
 217         unsigned short int r_status_notif;      /* removable media status notif. */
 218         unsigned short int security_status;     /* security status */
 219         unsigned short int vendor_spec129_159[31];
 220         unsigned short int reserved160_255[96];
 221 };
 222 
 223 struct ide_drv {
 224         int drive;                      /* master or slave */
 225         char *dev_name;
 226         unsigned char major;            /* major number */
 227         unsigned int flags;
 228         int minor_shift;                /* shift factor to get the real minor */
 229         int lba_cyls;
 230         int lba_heads;
 231         short int lba_factor;
 232         unsigned int nr_sects;          /* total sectors (LBA) */
 233         struct fs_operations *fsop;
 234         struct ide_drv_ident ident;
 235         struct partition part_table[NR_PARTITIONS];
 236 };
 237 
 238 struct ide {
 239         int channel;                    /* primary or secondary */
 240         int base;                       /* base address */
 241         int ctrl;                       /* control port address */
 242         short int irq;
 243         int current;                    /* avoids re-select the drive */
 244         struct resource resource;
 245         struct ide_drv drive[NR_IDE_DRVS];
 246 };
 247 
 248 extern struct ide ide_table[NR_IDE_CTRLS];
 249 
 250 extern int ide0_need_reset;
 251 extern int ide0_wait_interrupt;
 252 extern int ide0_timeout;
 253 extern int ide1_need_reset;
 254 extern int ide1_wait_interrupt;
 255 extern int ide1_timeout;
 256 
 257 void irq_ide0(int, struct sigcontext *);
 258 void ide0_timer(unsigned int);
 259 void irq_ide1(int, struct sigcontext *);
 260 void ide1_timer(unsigned int);
 261 
 262 void ide_error(struct ide *, int);
 263 void ide_delay(void);
 264 void ide_wait400ns(struct ide *);
 265 int ide_drvsel(struct ide *, int, int, unsigned char);
 266 int ide_softreset(struct ide *);
 267 
 268 struct ide * get_ide_controller(__dev_t);
 269 int get_ide_drive(__dev_t);
 270 
 271 int ide_open(struct inode *, struct fd *);
 272 int ide_close(struct inode *, struct fd *);
 273 int ide_read(__dev_t, __blk_t, char *, int);
 274 int ide_write(__dev_t, __blk_t, char *, int);
 275 int ide_ioctl(struct inode *, int, unsigned long int);
 276 
 277 void ide_init(void);
 278 
 279 #endif /* _FIWIX_IDE_H */

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