root/include/fiwix/serial.h

/* */

INCLUDED FROM

   1 /*
   2  * fiwix/include/fiwix/serial.h
   3  *
   4  * Copyright 2020-2021, Jordi Sanfeliu. All rights reserved.
   5  * Distributed under the terms of the Fiwix License.
   6  */
   7 
   8 #ifndef _FIWIX_SERIAL_H
   9 #define _FIWIX_SERIAL_H
  10 
  11 #define SERIAL4_IRQ     4       /* IRQ for serial ports 1 and 3 */
  12 #define SERIAL3_IRQ     3       /* IRQ for serial ports 2 and 4 */
  13 
  14 #define NR_SERIAL       4       /* maximum number of serial ttys */
  15 #define SERIAL_MAJOR    4       /* major number for /dev/ttyS[n] */
  16 #define SERIAL_MINORS   NR_SERIAL
  17 #define SERIAL_MSF      6       /* serial minor shift factor */
  18 
  19 /* UART registers */
  20 #define UART_TD         0       /* W:  Transmitter Holding Buffer */
  21 #define UART_RD         0       /* R:  Receiver Buffer */
  22 #define UART_DLL        0       /* RW: Divisor Latch Low Byte */
  23 #define UART_DLH        1       /* RW: Divisor Latch High Byte */
  24 #define UART_IER        1       /* RW: Interrupt Enable Register */
  25 #define UART_IIR        2       /* R:  Interrupt Identification Register */
  26 #define UART_FCR        2       /* W:  FIFO Control Register */
  27 #define UART_LCR        3       /* RW: Line Control Register */
  28 #define UART_MCR        4       /* RW: Modem Control Register */
  29 #define UART_LSR        5       /* R:  Line Status Register */
  30 #define UART_MSR        6       /* R:  Modem Status Register */
  31 #define UART_SR         7       /* RW: Scratch Register */
  32 
  33 /* Interrupt Enable Register */
  34 #define UART_IER_RDAI   0x1     /* enable Received Data Available Interrupt  */
  35 #define UART_IER_THREI  0x2     /* enable Transmitter Holding Register Empty Interrupt */
  36 #define UART_IER_RLSI   0x4     /* enable Receiver Line Status Interrupt */
  37 #define UART_IER_MSI    0x8     /* enable Modem Status Interrupt */
  38 
  39 /* Interrupt Identification Register */
  40 #define UART_IIR_NOINT  0x01    /* no interrupts pending */
  41 #define UART_IIR_MKINT  0x06    /* mask all interrupt flags */
  42 #define UART_IIR_MSI    0x00    /* Modem Status Interrupt */
  43 #define UART_IIR_THREI  0x02    /* Transmitter Holding Register Empty Interrupt */
  44 #define UART_IIR_RDAI   0x04    /* Received Data Available Interrupt */
  45 #define UART_IIR_RLSI   0x06    /* Receiver Line Status Interrupt */
  46 #define UART_IIR_FIFOTO 0xC0    /* FIFO TimeOut interrupt */
  47 #define UART_IIR_FIFO64 0x20    /* 64 byte FIFO enabled (16750 only) */
  48 #define UART_IIR_FIFO   0x40    /* FIFO is enabled (still needs bit #7 on) */
  49 #define UART_IIR_FIFOKO 0x80    /* FIFO is enabled, but unusable */
  50 
  51 /* FIFO Control Register */
  52 #define UART_FCR_FIFO   0x07    /* enable FIFO (clear receive and transmit) */
  53 #define UART_FCR_CRCVR  0x02    /* clear receiver */
  54 #define UART_FCR_CXMTR  0x04    /* clear transmitter */
  55 #define UART_FCR_DMA    0x08    /* DMA mode select */
  56 #define UART_FCR_FIFO64 0x20    /* enable 64 byte FIFO (16750 only) */
  57 #define UART_FCR_FIFO14 0xC0    /* set to 14 bytes 'trigger level' FIFO */
  58 
  59 /* Line Control Register */
  60 #define UART_LCR_WL5    0x00    /* word length 5 bits */
  61 #define UART_LCR_WL6    0x01    /* word length 6 bits */
  62 #define UART_LCR_WL7    0x02    /* word length 7 bits */
  63 #define UART_LCR_WL8    0x03    /* word length 8 bits */
  64 #define UART_LCR_2STB   0x04    /* 2 stop bits */
  65 #define UART_LCR_1STB   0x00    /* 1 stop bit */
  66 #define UART_LCR_NP     0x00    /* no parity */
  67 #define UART_LCR_OP     0x08    /* odd parity */
  68 #define UART_LCR_EP     0x18    /* even parity */
  69 #define UART_LCR_SBRK   0x40    /* Set Break enable */
  70 #define UART_LCR_DLAB   0x80    /* Divisor Latch Access Bit */
  71 
  72 /* Modem Control Register */
  73 #define UART_MCR_DTR    0x1     /* Data Terminal Ready */
  74 #define UART_MCR_RTS    0x2     /* Request To Send */
  75 #define UART_MCR_OUT2   0x8     /* Auxiliary Output 2 */
  76 
  77 /* Line Status Register */
  78 #define UART_LSR_RDA    0x01    /* Received Data Available */
  79 #define UART_LSR_OE     0x02    /* Overrun Error */
  80 #define UART_LSR_PE     0x04    /* Parity Error */
  81 #define UART_LSR_FE     0x08    /* Framing Error */
  82 #define UART_LSR_BI     0x10    /* Break Interrupt */
  83 #define UART_LSR_THRE   0x20    /* Transmitter Holding Register Empty */
  84 #define UART_LSR_EDHR   0x40    /* Empty Data Holding Registers TD and SH */
  85 #define UART_LSR_EFIFO  0x80    /* Error in Received FIFO */
  86 
  87 
  88 #define UART_FIFO_SIZE  16      /* 16 bytes */
  89 #define UART_HAS_FIFO   0x02    /* has FIFO working */
  90 #define UART_IS_8250    0x04    /* is a 8250 chip */
  91 #define UART_IS_16450   0x08    /* is a 16450 chip */
  92 #define UART_IS_16550   0x10    /* is a 16550 chip */
  93 #define UART_IS_16550A  0x20    /* is a 16550A chip */
  94 
  95 struct serial {
  96         short int addr;         /* port I/O address */
  97         char irq;
  98         int baud;
  99         char *name;
 100         short int lctrl;        /* line control flags (8N1, 7E2, ...) */
 101         int flags;
 102         struct tty *tty;
 103         struct serial *next;
 104 };
 105 
 106 int serial_open(struct tty *);
 107 int serial_close(struct tty *);
 108 int serial_ioctl(struct tty *, int, unsigned long int);
 109 void serial_write(struct tty *);
 110 void irq_serial(int, struct sigcontext *);
 111 void irq_serial_bh(void);
 112 void serial_init(void);
 113 
 114 #endif /* _FIWIX_SERIAL_H */

/* */